1. Field of the Invention
The present invention relates to a multiple instruction parallel issue/execution management system, provided in a superscalar processor of dynamically issuing a plurality of instructions in parallel and of executing the plurality of instructions in parallel, and for managing the issuing and execution of the plurality of instructions.
2. Description of Related Art
A technology called a "superscalar" is widely used for elevating the performance of a general-purpose processor, in particular, a microprocessor. The superscalar technology is featured so that, when individual instructions included in an instruction string are sequentially fetched, decoded, issued and executed, a plurality of instructions are fetched and decoded in parallel, and from decoded instructions, a plurality of executable instructions are dynamically designated and issued to a plurality of arithmetic and logic units and a memory access unit in parallel so that the instructions are executed in parallel. The conventional superscalar technology is described in detail by Mike Johnson, "Superscalar Microprocessor Design", published by Prentice Hall.
In the conventional superscalar microprocessor using the superscalar technology, a multiple instruction parallel issue management unit and a multiple instruction parallel execution management unit have an extremely important role for realizing the above mentioned parallel processing. The multiple instruction parallel issue management unit is called a "reservation station", and the multiple instruction parallel execution management unit is called a "reorder buffer".
The multiple instruction parallel issue management unit performs an operation of temporarily holding a plurality of decoded instructions, discriminating whether or not each of the held decoded instructions is issuable, and selecting and issuing some number of instructions from issuable instructions, and continuing to hold non-issuable instructions in the multiple instruction parallel issue management unit to re-check whether or not each of the instructions are issuable.
Referring to FIG. 30, there is shown a block diagram illustrating a fundamental construction of the prior art multiple instruction parallel issue/execution management unit. The shown multiple instruction parallel issue/execution management unit comprises a plurality of not-yet-issued instruction entries 2501 and an issue control unit 2502. Each of the not-yet-issued instruction entries 2501 includes an instruction tag field 25011, an instruction code field 25012, a first operand/tag field 25013, a second operand/tag field 25014, a comparator 25015, and another comparator 25016. Furthermore, the shown multiple instruction parallel issue/execution management unit comprises an instruction tag input terminal 2503, an instruction code input terminal 2504, a first operand/tag register input terminal 2505, a first tag comparison input terminal 2506, a second operand/tag register input terminal 2507, and a second tag comparison input terminal 2508. One instruction is temporarily held in each one not-yet-issued instruction entry.
In order to determine whether or not a given instruction is issuable, it is necessary to investigate whether or not all operands required by the given instruction are complete. In the prior art multiple instruction parallel issue management unit, whether or not all necessary input operands are complete, is discriminated by a parallel comparison using the comparators 25015 and 25016, as will be described below. Here, in the shown example, it is assumed that two input operands are used for one instruction.
In the instruction tag field 25011 of the not-yet-issued instruction entry 2501, an instruction tag inherent to the given instruction is stored. If input operands exist, the input operands are stored in the first operand/tag field 25013 and the second operand/tag field 25014, a comparator 25015, and another comparator 25016. If the input operands have not yet existed, instruction tags of instructions resultantly generating the input operands are stored in the first operand/tag field 25013 and the second operand/tag field 25014.
If execution of an instruction is completed, the instruction tag of the same instruction is supplied through the first tag comparison input terminal 2506 and the second tag comparison input terminal 2508 to the comparator 25015 and the comparator 25016 of all the not-yet-issued instruction entries 2501, respectively. These comparators 25015 and 25016 compare the input instruction tag with the values (the input operand or the instruction tag) stored in the first operand/tag field 25013 and the second operand/tag field 25014, respectively, in order to check whether or not both are consistent. Here, it is so set that the input operand and the instruction tag are never consistent.
If the result of comparison indicates consistency, since the result value of the instruction obtained by the completion of the execution of the instruction is supplied through the first operand/tag register input terminal 2505 and the second operand/tag register input terminal 2507, the result value is registered in the first operand/tag field 25013 or the second operand/tag field 25014. On the other hand, the issue control unit 2502 receives the result of comparison from the comparators 25015 and 25016, and discriminates whether or not all operands required by the respective instruction are complete.
As mentioned above, the multiple instruction parallel issue management unit of the prior art superscalar microprocessor discriminates whether or not the instruction is issuable, by the parallel comparison using the comparators 25015 and 25016. Incidentally, in the example shown in FIG. 30, one comparator 25015 and one comparator 25016 are provided for each one not-yet-issued instruction entry, but actually, for each one entry there are required the comparators of the number of instructions simultaneously executed in parallel.
On the other hand, the multiple instruction parallel execution management unit is constructions as follows: In order to ensure the order of instructions when the instructions are executed in the order different from the instruction fetch/decode order, the multiple instruction parallel execution management unit temporarily holds the result value of the instruction which has been executed but whose execution result has not yet been decided (called a "not-yet-decided result value" hereinafter), and supplies these not-yet-decided result values to the not-yet-issued instructions as an input operand.
Referring to FIG. 31, there is shown a block diagram illustrating a fundamental construction of the prior art multiple instruction parallel execution management unit. The shown multiple instruction parallel execution management unit includes a plurality of executed instruction entries 2601 and an execution control unit 2602. Each of the executed instruction entries 2601 includes a result value field 26011, an instruction tag field 26012, a register number field 26013, and three comparators 26014, 26015 and 26016. The shown multiple instruction parallel execution management unit further includes a result value input terminal 2603, an instruction tag registration input terminal 2604, an in instruction tag comparison input terminal 2605, a register number registration input terminal 2606, a first input terminal 26071 for register number comparison, and a second input terminal 26072 for register number comparison, a first operand/tag output terminal 26081, a second operand/tag output terminal 26082, a result value output terminal 26091 and a register number output terminal 26092. For each one executed instruction entry 2601, a not-yet-decided result value of one executed instruction is temporarily stored.
When an instruction requires an input operand for a register file, the multiple instruction parallel execution management unit investigates whether or not the required input operand is temporarily stored within the multiple instruction parallel execution management unit as a not-yet-decided result value with having not yet been written into the register file, and supplies the not-yet-decided result value as the input operand for the instruction if necessary. This operation is realized in the prior art multiple instruction parallel execution management unit by a parallel comparison using the comparators 26015 and 26016, as will be described below:
In the result value field 26011 of the executed instruction entry 2601, the not-yet-decided result value is stored, and the instruction tag is stored in the instruction field 26012. In the register number field 26013, the register number to be written is stored. When an instruction requires two input operands, the register numbers from which the required two input operands are to be read out, are respectively supplied through the register number comparison first input terminal 26071 and the register number comparison second input terminal 26072 to the comparators 26015 and 26016 of all the entries. Each of these comparators 26015 and 26016 compares a corresponding input register number with the register number stored in the register number field 26013.
For all the entries, the execution control unit 2602 investigates whether or not the register number consistency is detected as the result of the comparison. If a plurality of consistency results are obtained for one input operand, it is discriminated that the register number consistency is detected in the entry storing the newest instruction. From the executed instruction entry 2601 which is discriminated to be consistent with the respective input operand, the result value and the instruction tag are read out and outputted through the first operand/tag output terminal 26081 and the second operand/tag output terminal 26082.
When execution of an instruction has been completed, the comparator 26014 is used for determining into which of the executed instruction entry 2601 the not-yet-decided result value of the executed instruction is stored. The determination is conducted by comparing the instruction tag of the executed instruction with the instruction tag previously stored in the instruction tag field 26012 of each entry by use of the comparator 26014 in parallel, in order to investigate the executed instruction entry consistent with the instruction tag of the executed instruction. In addition, when the execution of an instruction is decided, the result value and the register number of that instruction are outputted from the multiple instruction parallel execution management unit through the result output terminal 26091 and the register number output terminal 26092 to the register file.
As mentioned above, the multiple instruction parallel execution management unit of the prior art superscalar microprocessor discriminates whether or not the not-yet-decided result value is supplied as the input operand for the not-yet-issued instruction, by a parallel comparison using the comparators 26015 and 20016 of all the executed instruction entries. Incidentally, in the shown example, one comparator 26014, one comparator 26015 and one comparator 26016 are provided for each one executed instruction entry. However, for each one executed instruction entry, there are required the comparators 26014 of the number corresponding to the number of instructions, executions of which are simultaneously completed, and also there are required the comparators 26015 and 26016 of the number corresponding to the number of instructions which are simultaneously decoded.
As mentioned above, the microprocessor based on the prior art superscalar technology, requires a large number of comparators in each of the multiple instruction parallel issue management unit and the multiple instruction parallel execution management unit, for the purpose of the parallel decoding, the parallel issuing and the parallel execution of a plurality of instructions.
For example, consider a microprocessor using the prior art superscalar based on the prior art superscalar technology and constructed to issue three instructions in parallel and to execute and complete the three instructions in parallel. The microprocessor having the comparators of the number required in this scale, is actually manufactured and used, although the design is considerably complicated. In this case, the number of the not-yet-issued instruction entries 2501 in the multiple instruction parallel issue management unit is required to be at least 8, and the number of the executed instruction entries 2601 in the multiple instruction parallel execution management unit, is required to be at least 16. Therefore, the number of required comparators is 48 (=2.times.8.times.3) in the multiple instruction parallel issue management unit, and 144 (=3.times.16.times.3) in the multiple instruction parallel execution management unit.
Furthermore, consider a microprocessor using the prior art superscalar based on the prior art superscalar technology and constructed to issue nine instructions (which are three times the number of instructions processed in the above example) in parallel and to execute and complete the nine instructions in parallel. In this case, in proportion to the number of instructions issued and executed in parallel, it is necessary to increase the number of the not-yet-issued instruction entries 2501 in the multiple instruction parallel issue management unit and the number of the executed instruction entries 2601. For example, the number of the not-yet-issued instruction entries 2501 is required to be at least 24, and the number of the executed instruction entries 2601 is required to be at least 48. Therefore, the total number of required comparators is 432 (=2.times.24.times.9) in the multiple instruction parallel issue management unit, and 1296 (=3.times.48.times.9) in the multiple instruction parallel execution management unit.
As seen from the above, the number of the comparators in the multiple instruction parallel issue management unit and the multiple instruction parallel execution management unit has the nature of increasing abruptly substantially in proportion to a square of the number of instructions which are, in parallel, issued, executed and complete in execution. Incidentally, the number of instructions issued in parallel, the number of instructions executed in parallel and the number of instructions completed in execution in parallel, are set to be same or the substantially the same.
As described above, the microprocessor based on the prior art superscalar technology, requires a large number of comparators in each of the multiple instruction parallel issue management unit and the multiple instruction parallel execution management unit, in order to decode a plurality of instructions in parallel, to issue a plurality of instructions in parallel, and to execute a plurality of instructions in parallel. Because of this large number of comparators and the control circuits therefor, the multiple instruction parallel issue management unit and the multiple instruction parallel execution management unit in the microprocessor based on the prior art superscalar technology, are not only extremely complicated in construction but also large in circuit scale.
In addition, since a large amount of comparing operations are executed simultaneously in parallel, a large amount of electric power is consumed.
Furthermore, since the number of the comparators in the multiple instruction parallel issue management unit and the multiple instruction parallel execution management unit has the nature of increasing abruptly substantially in proportion to a square of the number of instructions which are, in parallel, issued, executed and complete in execution, if attempt is made to elevate the degree of parallelism in processing, the degree of complication in the control circuits and in wiring also abruptly increases with increase of the number of the comparators, and the delay time correspondingly increases. These problems are a serious problem in improving the architecture of the microprocessor using the superscalar technology, and in elevating the degree of parallelism in processing.
Elevation of the degree of parallelism in processing is the most important factor in increasing the processing performance of the microprocessor using the superscalar technology. However, because of the above mentioned reason, it was difficult to manufacture a processor capable of executing ten or more instructions in parallel.